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LHF64P01 ? handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. ? when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. ? please direct all queries regarding the products covered herein to a sales representative of the company. rev. 0.06
LHF64P01 1 contents pa ge 56-lead tsop (normal bend) pinout ....................... 3 pin descriptions.......................................................... 4 ce0, ce1, ce2 truth table ....................................... 5 memory map .............................................................. 6 identifier codes address ............................................ 7 otp block address map............................................ 8 bus operation............................................................. 9 command definitions .............................................. 10 functions of block lock .......................................... 12 status register definition......................................... 13 extended status register definition ........................ 14 sts configuration definition .................................. 15 page 1 electrical specifications ........................................ 16 1.1 absolute maximum ratings........................... 16 1.2 operating conditions ..................................... 16 1.2.1 capacitance.............................................. 17 1.2.2 ac input/output test conditions............ 17 1.2.3 dc characteristics................................... 18 1.2.4 ac characteristics - read-only operations .............................. 20 1.2.5 ac characteristics - write operations.... 24 1.2.6 reset operations...................................... 26 1.2.7 block erase, (page buffer) program and block lock configuration performance.............................................. 27 2 related document information ............................. 28 3 package and packing specification........................ 29 rev. 0.06
LHF64P01 2 lh28f640spht-ptl12 64mbit (4mbit 16/8mbit 8) page mode flash memory ? 64-mbit density ? bit organization 8/ 16 ? high performance page mode reads for memory array 120/25ns 4-word/ 8-byte page mode ? v cc =2.7v-3.6v operation v ccq for input/output power supply isolation automatic power savings mode reduces i ccr in static mode ? otp (one time program) block 4-word/ 8-byte factory-programmed area 3963-word/ 7926-byte user-programmable area ? high performance program with page buffer 16-word/ 32-byte page buffer page buffer program time 12.5 s/byte (typ.) ? operating temperature -40 c to +85 c ? symmetrically-blocked architecture sixty-four 64-kword/ 128-kbyte blocks ? enhanced data protection features individual block lock absolute protection with v pen v penlk block erase, (page buffer) program lockout during power transitions ? automated erase/program algorithms program time 210 s (typ.) block erase time 1s (typ.) ? cross-compatible command support basic command set common flash interface (cfi) ? extended cycling capability minimum 100,000 block erase cycles ? 56-lead tsop (normal bend) ? cmos process (p-type silicon substrate) ? etox tm* flash technology ? not designed or rated as radiation hardened the product, which is page mode flash memory, is a high density, low cost, nonvolatile read/write storage solution for a wide range of applications. the product can operate at v cc =2.7v-3.6v and v pen =2.7v-3.6v the product supports high performance page mode. it allows code execution directly from flash, thus eliminating time consuming wait states. fast program capability is provided through the use of high speed page buffer program. the block locking scheme is available for memory array and this scheme provides maximum flexibility for safe nonvolatile code and data storage. otp (one time program) block provides an area to store security code and to protect its code. * etox is a trademark of intel corporation. rev. 0.06
LHF64P01 3 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 56-lead tsop standard pinout 14mm x 20mm top view a 19 a 18 a 17 a 16 v cc a 15 a 14 a 13 a 12 ce 0 v pen rp# a 11 a 10 a 9 a 8 gnd a 7 a 6 a 5 a 4 a 3 a 2 a 1 we# oe# sts dq 15 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v ccq gnd dq 11 dq 3 dq 10 v cc dq 9 dq 1 dq 8 dq 0 a 0 byte# nc 1 2 3 4 56 55 54 53 a 22 ce 1 a 21 a 20 ce 2 dq 2 gnd nc figure 1. 56-lead tsop (normal bend) pinout rev. 0.06
LHF64P01 4 table 1. pin descriptions symbol type name and function a 0 input address inputs: lowest address input in byte mode (byte#=v il : 8 bit). address is internally latched during an erase or a program cycle. this pin is not used in word mode (byte#=v ih : 16 bit) a 22 -a 1 input address inputs: inputs for addresses during read, erase and program operations. addresses are internally latched during an erase or a program cycle. dq 15 -dq 0 input/ output data inputs/outputs: inputs data and commands during cui (command user interface) write cycles, outputs data during memory array, status register, query code, identifier code reads. data pins float to high-impedance (high z) when the chip or outputs are deselected. data is internally latched during an erase or program cycle. dq 15 -dq 8 pins are not used in byte mode (byte#=v il : 8 bit). ce 0 , ce 1 , ce 2 input chip enable: activates the device ? s control logic, input buffers, decoders and sense amplifiers. when the device is de-selected, power consumption reduces to standby levels. refer to table 2 to determine whether the device is selected or de-selected depending on the state of ce 0 , ce 1 and ce 2 . rp# input reset: when low (v il ), rp# resets internal automation and inhibits erase and program operations, which provides data protection. rp#-high (v ih ) enables normal operation. after power-up or reset mode, the device is automatically set to read array mode. rp# must be low during power-up/down. oe# input output enable: gates the device ? s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the first edge of ce 0 , ce 1 or ce 2 that disables the device or the rising edge of we# (whichever occurs first). sts open drain output status: indicates the status of the internal wsm (write state machine). when configured in level mode (default mode), sts acts as a ry/by# pin (sts is v ol when the wsm is executing internal erase or program algorithms). when configured in one of its pulse modes, sts can pulse to indicate erase/program completion. refer to table 9 for sts configuration. byte# input byte enable: byte# v il places the device in byte mode ( 8). in this mode, dq 15 - dq 8 is floated (high z) and a 0 is the lowest address input. byte# v ih places the device in word mode ( 16) and a 1 is the lowest address input. v pen input monitoring power supply voltage: v pen is not used for power supply pin. with v pen v penlk , block erase, (page buffer) program, block lock configuration and otp program cannot be executed and should not be attempted. v cc supply device power supply (2.7v-3.6v): with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (refer to dc characteristics) produce spurious results and should not be attempted. v ccq supply input/output power supply (2.7v-3.6v): power supply for all input/output pins. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated. rev. 0.06
LHF64P01 5 note: 1. for single-chip applications, ce 1 and ce 2 can be connected to gnd. table 2. ce 0 , ce 1 , ce 2 truth table (1) ce 2 ce 1 ce 0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled rev. 0.06
LHF64P01 6 64-kword/128-kbyte block 63 64-kword/128-kbyte block 62 64-kword/128-kbyte block 61 64-kword/128-kbyte block 60 64-kword/128-kbyte block 59 64-kword/128-kbyte block 58 64-kword/128-kbyte block 57 64-kword/128-kbyte block 56 64-kword/128-kbyte block 55 64-kword/128-kbyte block 54 64-kword/128-kbyte block 53 64-kword/128-kbyte block 52 64-kword/128-kbyte block 51 64-kword/128-kbyte block 50 64-kword/128-kbyte block 49 64-kword/128-kbyte block 48 64-kword/128-kbyte block 47 64-kword/128-kbyte block 46 64-kword/128-kbyte block 45 64-kword/128-kbyte block 44 64-kword/128-kbyte block 43 64-kword/128-kbyte block 42 64-kword/128-kbyte block 41 64-kword/128-kbyte block 40 64-kword/128-kbyte block 39 64-kword/128-kbyte block 38 64-kword/128-kbyte block 37 64-kword/128-kbyte block 36 64-kword/128-kbyte block 35 64-kword/128-kbyte block 34 64-kword/128-kbyte block 33 64-kword/128-kbyte block 32 64-kword/128-kbyte block 31 64-kword/128-kbyte block 30 64-kword/128-kbyte block 29 64-kword/128-kbyte block 28 64-kword/128-kbyte block 27 64-kword/128-kbyte block 26 64-kword/128-kbyte block 25 64-kword/128-kbyte block 24 64-kword/128-kbyte block 23 64-kword/128-kbyte block 22 64-kword/128-kbyte block 21 64-kword/128-kbyte block 20 64-kword/128-kbyte block 19 64-kword/128-kbyte block 18 64-kword/128-kbyte block 17 64-kword/128-kbyte block 16 64-kword/128-kbyte block 15 64-kword/128-kbyte block 14 64-kword/128-kbyte block 13 64-kword/128-kbyte block 12 64-kword/128-kbyte block 11 64-kword/128-kbyte block 10 64-kword/128-kbyte block 9 64-kword/128-kbyte block 8 64-kword/128-kbyte block 7 64-kword/128-kbyte block 6 64-kword/128-kbyte block 5 64-kword/128-kbyte block 4 64-kword/128-kbyte block 3 64-kword/128-kbyte block 2 64-kword/128-kbyte block 1 64-kword/128-kbyte block 0 [a 22 - a 1 ] [a 22 - a 1 ] [a 22 - a 0 ] [a 22 - a 0 ] 000000 020000 03ffff 01ffff 040000 05ffff 060000 07ffff 080000 09ffff 0a0000 0bffff 0c0000 0dffff 0e0000 0fffff 100000 11ffff 120000 13ffff 140000 15ffff 160000 17ffff 180000 19ffff 1a0000 1bffff 1c0000 1dffff 1e0000 1fffff 200000 21ffff 220000 23ffff 240000 25ffff 260000 27ffff 280000 29ffff 2a0000 2bffff 2e0000 2fffff 300000 31ffff 320000 33ffff 340000 35ffff 360000 37ffff 380000 39ffff 3a0000 3bffff 3c0000 3dffff 3e0000 3fffff 2c0000 2dffff 000000 010000 01ffff 00ffff 020000 02ffff 030000 03ffff 040000 04ffff 050000 05ffff 060000 06ffff 070000 07ffff 080000 08ffff 090000 09ffff 0a0000 0affff 0b0000 0bffff 0c0000 0cffff 0d0000 0dffff 0e0000 0effff 0f0000 0fffff 100000 10ffff 110000 11ffff 120000 12ffff 130000 13ffff 140000 14ffff 150000 15ffff 170000 17ffff 180000 18ffff 190000 19ffff 1a0000 1affff 1b0000 1bffff 1c0000 1cffff 1d0000 1dffff 1e0000 1effff 1f0000 1fffff 160000 16ffff 200000 210000 21ffff 20ffff 220000 22ffff 230000 23ffff 240000 24ffff 250000 25ffff 260000 26ffff 270000 27ffff 280000 28ffff 290000 29ffff 2a0000 2affff 2b0000 2bffff 2c0000 2cffff 2d0000 2dffff 2e0000 2effff 2f0000 2fffff 300000 30ffff 310000 31ffff 320000 32ffff 330000 33ffff 340000 34ffff 350000 35ffff 370000 37ffff 380000 38ffff 390000 39ffff 3a0000 3affff 3b0000 3bffff 3c0000 3cffff 3d0000 3dffff 3e0000 3effff 3f0000 3fffff 360000 36ffff 400000 420000 43ffff 41ffff 440000 45ffff 460000 47ffff 480000 49ffff 4a0000 4bffff 4c0000 4dffff 4e0000 4fffff 500000 51ffff 520000 53ffff 540000 55ffff 560000 57ffff 580000 59ffff 5a0000 5bffff 5c0000 5dffff 5e0000 5fffff 600000 61ffff 620000 63ffff 640000 65ffff 660000 67ffff 680000 69ffff 6a0000 6bffff 6e0000 6fffff 700000 71ffff 720000 73ffff 740000 75ffff 760000 77ffff 780000 79ffff 7a0000 7bffff 7c0000 7dffff 7e0000 7fffff 6c0000 6dffff rev. 0.06 figure 2. memory map
LHF64P01 7 notes: 1. the address a 0 don't care. 2. "00h" is presented on dq 15 -dq 8 in word mode (byte#=v ih : 16 bit). 3. block address = the beginning location of a block address. dq 15 -dq 1 are reserved for future implementation. table 3. identifier codes address code address [a 22 -a 1 ] (1) data [dq 7 -dq 0 ] notes manufacturer code manufacturer code 000000h b0h 2 device code device code 000001h 17h 2 block lock configuration code block is unlocked block address + 2 dq 0 = 0 3 block is locked dq 0 = 1 3 rev. 0.06
LHF64P01 8 rev. 0.06 customer programmable area lock bit (dq 1 ) factory programmed area lock bit (dq 0 ) customer programmable area factory programmed area reserved for future implementation 000080h 000081h 000084h 000085h 000fffh [a 22 -a 1 ] (dq 15 -dq 2) 000100h 000102h 000109h 00010ah 001fffh [a 22 -a 0 ] figure 3. otp block address map (the area not specified in the above figure cannot be used.)
LHF64P01 9 rev. 0.06 notes: 1. refer to dc characteristics. when v pen v penlk , memory contents can be read, but cannot be altered. 2. x can be v il or v ih for control pins and addresses, and v penlk or v penh for v pen . refer to dc characteristics for v penlk and v penh voltages. 3. refer to table 2 to determine whether the device is selected or de-selected depending on the state of ce 0 , ce 1 and ce 2 . 4. dq refers to dq 15 -dq 0 in word mode (byte#=v ih : 16 bit) and dq 7 -dq 0 in byte mode (byte#=v il : 8 bit). 5. rp# at gnd0.2v ensures the lowest power consumption. 6. command writes involving block erase, (page buffer) program, block lock configuration or otp program are reliably executed when v pen =v penh and v cc =2.7v-3.6v. 7. refer to table 5 for valid d in during a write operation. 8. never hold oe# low and we# low at the same timing. 9. refer to appendix of lh28f640sp series for more information about query code. 10. sts is v ol when the wsm (write state machine) is executing internal block erase, (page buffer) program or otp program algorithms. it is high z during when the wsm is not busy, in block erase suspend mode (with program and page buffer program inactive), (page buffer) program suspend mode, or reset mode. table 4. bus operation (1, 2) mode notes rp# ce 0,1,2 (3) oe# we# address v pen dq (4) sts (10) read array 8 v ih enabled v il v ih xx d out x output disable v ih enabled v ih v ih xxhigh zx standby v ih disabled x x x x high z x reset 5 v il xxxxxhigh zhigh z read identifier codes/otp 8 v ih enabled v il v ih refer to table 3 x refer to table 3 x read query 8,9 v ih enabled v il v ih see appendix x see appendix x write 6,7,8 v ih enabled v ih v il xx d in x
LHF64P01 10 notes: 1. bus operations are defined in table 4. 2. x=any valid address within the device. ia=identifier codes address (refer to table 3). qa=query codes address. refer to appendix of lh28f640sp series for details. ba=address within the block for block erase, page buffer program or set block lock bit. wa=address of memory location for the program command. oa=address of otp block to be read or programmed (refer to figure 3). 3. the upper byte of the data bus (dq 15 -dq 8 ) during command writes is ignored in word mode (byte#=v ih : 16 bit). id=data to be read from identifier codes. (refer to table 3). qd=data to be read from query database. refer to appendix of lh28f640sp series for details. srd=data to be read from status register. refer to table 7 for a description of the status register bits. wd=data to be programmed at location wa. data is latched on the first edge of ce 0 , ce 1 or ce 2 that disables the device or the rising edge of we# (whichever occurs first) during command write cycles. n-1=n is the number of the words /bytes to be loaded into a page buffer. od=data within otp block. data is latched on the first edge of ce 0 , ce 1 or ce 2 that disables the device or the rising edge of we# (whichever occurs first) during command write cycles. cc= sts configuration code (refer to table 9). 4. following the read identifier codes/otp command, read operations access manufacturer code, device code, block lock configuration code and the data within otp block (refer to table 3). the read query command is available for reading cfi (common flash interface) information. 5. block erase or (page buffer) program cannot be executed when the selected block is locked. unlocked block can be erased or programmed when rp# is v ih . 6. either 40h or 10h are recognized by the cui (command user interface) as the program setup. 7. following the third bus cycle, write the program sequential address and data of "n" times. finally, write the any valid address within the block to be programmed and the confirm command (d0h). table 5. command definitions (10) command bus cycles req ? d notes first bus cycle second bus cycle oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array 1 write x ffh read identifier codes/otp 2 4 write x 90h read ia or oa id or od read query 2 4 write x 98h read qa qd read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write ba 20h write ba d0h program 2 5,6 write x 40h or 10h write wa wd page buffer program 4 5,7 write ba e8h write ba n-1 block erase and (page buffer) program suspend 1 8 write x b0h block erase and (page buffer) program resume 1 8 write x d0h sts configuration 2 write x b8h write x cc set block lock bit 2 write x 60h write ba 01h clear block lock bits 2 9 write x 60h write x d0h otp program 2 write x c0h write oa od rev. 0.06
LHF64P01 11 refer to appendix of lh28f640sp series for details. 8. if both block erase operation and (page buffer) program operation are suspended, the suspended (page buffer) program operation is resumed when writing the block erase and (page buffer) program resume (d0h) command. 9. following the clear block lock bits command, all the blocks are unlocked at a time. 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used. rev. 0.06
LHF64P01 12 notes: 1. selected block is locked by the set block lock bit command. following the clear block lock bits command, all the blocks are unlocked at a time. 2. locked and unlocked states remain unchanged even after power-up/down and device reset. 3. after writing the read identifier codes/otp command, read operation outputs the block lock bit status on dq 0 (refer to table 3). 4. erase and program are general terms, respectively, to express: block erase and (page buffer) program operations. table 6. functions of block lock (1), (2) dq 0 (3) state name erase/program allowed (4) 0 unlocked yes 1locked no rev. 0.06
LHF64P01 13 rev. 0.06 table 7. status register definition rrrrrrrr 15 14 13 12 11 10 9 8 wsms bess becbls pbpopsbls vpens pbpss dps r 76543210 sr.15 - sr.8 = reserved for future enhancements (r) sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = block erase and clear block lock bits status (becbls) 1 = error in block erase or clear block lock bits 0 = successful block erase or clear block lock bits sr.4 = (page buffer) program, otp program and set block lock bit status (pbpopsbls) 1 = error in (page buffer) program, otp program or set block lock bit 0 = successful (page buffer) program, otp program or set block lock bit sr.3 = v pen status (vpens) 1 = v pen low detect, operation abort 0 = v pen ok sr.2 = (page buffer) program suspend status (pbpss) 1 = (page buffer) program suspended 0 = (page buffer) program in progress/completed sr.1 = device protect status (dps) 1 = erase or program attempted on a locked block, operation abort 0 = unlocked sr.0 = reserved for future enhancements (r) notes: check sr.7 or sts to determine block erase, (page buffer) program, block lock configuration or otp program completion. sr.6 - sr.1 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, page buffer program, block lock configuration, sts configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v pen level. the wsm interrogates and indicates the v pen level only after block erase, (page buffer) program, set block lock bit, clear block lock bits or otp program command sequences. sr.3 is not guaranteed to report accurate feedback when v pen v penh or v penlk . sr.1 does not provide a continuous indication of block lock bit. the wsm interrogates the block lock bit only after block erase, (page buffer) program or otp program command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. reading the block lock configuration codes after writing the read identifier codes/ otp command indicates block lock bit status. sr.15 - sr.8 and sr.0 are reserved for future use and should be masked out when polling the status register.
LHF64P01 14 table 8. extended status register definition rrrrrrrr 15 14 13 12 11 10 9 8 smsrrrrrrr 76543210 xsr.15-8 = reserved for future enhancements (r) xsr.7 = state machine status (sms) 1 = page buffer program available 0 = page buffer program not available xsr.6-0 =reserved for future enhancements (r) notes: after issue a page buffer program command (e8h), xsr.7="1" indicates that the entered command is accepted. if xsr.7 is "0", the command is not accepted and a next page buffer program command (e8h) should be issued again to check if page buffer is available or not. xsr.15-8 and xsr.6-0 are reserved for future use and should be masked out when polling the extended status register. rev. 0.06
LHF64P01 15 rev. 0.06 note: 1. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250ns. table 9. sts configuration definition (1) rrrrrrrr 15 14 13 12 11 10 9 8 rrrrrrcccc 76543210 dq 15 -dq 2 = reserved for future enhancements (r) dq 1 -dq 0 = sts configuration code (cc) 00 = level mode: ry/by# indication. (default) 01 = pulse mode on erase complete. 10 = pulse mode on program complete. 11 = pulse mode on erase or program complete. in sts configuration = "00", sts is v ol when the wsm is executing internal erase or program algorithms. sts configuration codes "01", "10" and "11" are all pulse modes such that the sts pin pulses low then high when the operation indicated by the configuration code is completed. notes: after power-up or device reset, sts configuration is set to "00". sts configuration 00 the output of the sts pin is the control signal to prevent accessing a flash memory while the internal wsm is busy (sr.7="0"). sts configuration 01 the output of the sts pin is the control signal to indicate that the erase operation is completed and the flash memory is available for the next operation. sts configuration 10 the output of the sts pin is the control signal to indicate that the program operation is completed and the flash memory is available for the next operation. sts configuration 11 the output of the sts pin is the control signal to indicate that the erase or program operation is completed and the flash memory is available for the next operation.
LHF64P01 16 1 electrical specifications 1.1 absolute maximum ratings * operating temperature during read, erase and program ...-40 c to +85 c (1) storage temperature during under bias............................... -40 c to +85 c during non bias................................ -65 c to +125 c voltage on any pin (except v cc , v ccq and v pen ) ................................................... -0.5v to v ccq +0.5v (2) v cc and v ccq supply voltage .......... -0.2v to +3.9v (2) v pen supply voltage.......................... -0.2v to +3.9v (2) output short circuit current ........................... 100ma (3) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc , v ccq and v pen pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. output shorted for no more than one second. no more than one output shorted at a time. rev. 0.06 1.2 operating conditions notes: 1. refer to dc characteristics tables for voltage range-specific specification. 2. v cc and v ccq should be the same voltage. symbol parameter notes min. typ. max. unit test conditions t a operating temperature -40 +25 +85 c ambient temperature v cc v cc supply voltage 1, 2 2.7 3.0 3.6 v v ccq i/o supply voltage 1, 2 2.7 3.0 3.6 v v penh v pen voltage 1 2.7 3.0 3.6 v block erase cycling: v pen =v penh 100,000 cycles
LHF64P01 17 test points v ccq /2 v ccq /2 input v ccq 0.0 output ac test inputs are driven at v ccq (min) for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends at v ccq /2. input rise and fall times (10% to 90%) < 5ns. worst case speed conditions are when v cc =v cc (min). device under test r l =3.3k ? c l v ccq (min)/2 out cl includes jig capacitances. 1n914 figure 5. transient equivalent testing load circuit rev. 0.06 table 10. configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.6v 30 1.2.2 ac input/output test conditions 1.2.1 capacitance (1) (t a = + 25 c, f=1mhz) note: 1. sampled, not 100% tested. symbol parameter min. typ. max. unit condition c in input capacitance 68pf v in =0.0v c out output capacitance 812pf v out =0.0v figure 4. transient input/output reference waveform for v cc =2.7v-3.6v
LHF64P01 18 rev. 0.06 1.2.3 dc characteristics v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions i li input load current 1 -1 +1 a v cc =v cc max., v ccq =v ccq max., v in /v out =v ccq or gnd i lo output leakage current 1 -10 +10 a i ccs v cc standby current 1, 2, 8 50 120 a cmos inputs, v cc =v cc max., v ccq =v ccq max., device is disabled (refer to table 2), rp#=v ccq 0.2v 0.71 2 ma ttl inputs, v cc =v cc max., v ccq =v ccq max., device is disabled (refer to table 2), rp#=v ih i ccas v cc automatic power savings current 1, 2, 5 50 120 a cmos inputs, v cc =v cc max., v ccq =v ccq max., device is enabled (refer to table 2) i ccd v cc reset current 150120 a rp#=gnd0.2v i out (sts)=0ma i ccr average v cc page mode read current 4 word/ 8 byte read 1, 2 15 20 ma cmos inputs, v cc =v cc max., v ccq =v ccq max., device is enabled (refer to table 2), f=5mhz, i out =0ma 1, 2 24 29 ma cmos inputs, v cc =v cc max., v ccq =v ccq max., device is enabled (refer to table 2), f=33mhz, i out =0ma average v cc read current 1 word/ 1 byte read 1, 2 40 50 ma cmos inputs, v cc =v cc max., v ccq =v ccq max., device is enabled (refer to table 2), f=5mhz, i out =0ma i ccw v cc (page buffer) program, set block lock bit current 1, 2, 6 35 60 ma cmos inputs, v pen =v penh 1, 2, 6 40 70 ma ttl inputs, v pen =v penh
LHF64P01 19 notes: 1. all currents are in rms unless otherwise noted. typical values are the reference values at v cc =3.0v, v ccq =3.0v and t a =+25 c unless v cc is specified. 2. cmos inputs are either v ccq 0.2v or gnd0.2v. ttl inputs are either v il or v ih . 3. i ccws and i cces are specified with the device de-selected. if read or (page buffer) program is executed while in block erase suspend mode, the device ? s current draw is the sum of i cces and i ccr or i ccw . if read is executed while in (page buffer) program suspend mode, the device ? s current draw is the sum of i ccws and i ccr . 4. block erase, (page buffer) program, block lock configuration and otp program operations are inhibited when v pen v penlk or v cc v lko . these operations are not guaranteed outside the specified voltage (v cc =2.7v-3.6v and v pen =2.7v-3.6v). 5. the automatic power savings (aps) feature automatically places the device in power save mode after read cycle completion. standard address access timings (t avqv ) provide new data when addresses are changed. 6. sampled, not 100% tested. 7. v pen is not used for power supply pin. with v pen v penlk , block erase, (page buffer) program, block lock configuration and otp program operations are inhibited. 8. includes sts. i cce v cc block erase, clear block lock bits current 1, 2, 6 35 70 ma cmos inputs, v pen =v penh 1, 2, 6 40 80 ma ttl inputs, v pen =v penh i ccws i cces v cc (page buffer) program or block erase suspend current 1, 3 10 ma device is disabled (refer to table 2). v il input low voltage 6 -0.5 0.8 v v ih input high voltage 6 2.0 v ccq + 0.5 v v ol output low voltage 6, 8 0.4 v v cc =v cc min., v ccq =v ccq min., i ol =2ma 0.2 v v cc =v cc min., v ccq =v ccq min., i ol =100 a v oh output high voltage 6, 8 0.85 v ccq v v cc =v cc min., v ccq =v ccq min., i oh =-1.5ma v ccq -0.2 v v cc =v cc min., v ccq =v ccq min., i oh =-100a v penlk v pen lockout voltage during normal operations 4, 6, 7 1.0 v v penh v pen voltage during block erase, (page buffer) program, set block lock bit, clear block lock bits or otp program operations 4, 7 2.7 3.0 3.6 v v lko v cc lockout voltage 42.0 v v cc =2.7v-3.6v symbol parameter notes min. typ. max. unit test conditions rev. 0.06 dc characteristics (continued)
LHF64P01 20 1.2.4 ac characteristics - read-only operations (1) notes: 1. refer to ac input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. sampled, not 100% tested. 3. oe# may be delayed up to t elqv ? t glqv after the first edge of ce 0 , ce 1 or ce 2 that enables the device (refer to table 2) without impact to t elqv . 4. the timing is defined from the first edge of ce 0 , ce 1 or ce 2 that enables the device. 5. the timing is defined from the first edge of ce 0 , ce 1 or ce 2 that disables the device. t a =-40 c to +85 c v cc 3.0v-3.6v 2.7v-3.6v v ccq 3.0v-3.6v 2.7v-3.6v symbol parameter notes min. max. min. max. unit t avav read cycle time 120 120 ns t av q v address to output delay 120 120 ns t elqv ce x to output delay 3, 4 120 120 ns t apa page address access time 25 30 ns t glqv oe# to output delay 3 25 30 ns t phqv rp# high to output delay 180 180 ns t elqx ce x to output in low z 2, 4 0 0 ns t glqx oe# to output in low z 2 0 0 ns t ehqz ce x to output in high z 2, 5 35 35 ns t ghqz oe# to output in high z 2 15 15 ns t oh output hold from first occurring address, ce x or oe# change 2, 5 0 0 ns t elfl /t elfh cex setup to byte# going low or high 2, 4 10 10 ns t flqv /t fhqv byte# to output delay 1000 1000 ns t flqz /t fhqz byte# to output in high z 2 1000 1000 ns rev. 0.06
LHF64P01 21 t avqv t ehqz t ghqz t elqv t phqv t glqv t oh v ih v il disabled (v ih ) enabled (v il ) v ih v il v ih v il v oh v ol v ih v il (p) (d/q) (w) (g) (e) (a) a 22-0 dq 15-0 ce x oe# we# rp# high z t elqx valid output valid address t glqx v ih v il (f) byte# t avav t flqz /t fhqz t flqv /t fhqv t elfl /t elfh figure 6. ac waveform for 1-word/ 1-byte read operations (status register, identifier codes, otp block or query code) rev. 0.06 note: 1. status register, identifier codes, otp block and query code can only be read in 1-word/ 1-byte read operations.
LHF64P01 22 t avqv t elqv t ehqz t ghqz t oh t apa t glqv t phqv high z v ih v il v ih v il v oh v ol v ih v il (p) (w) (g) v ih v il (a) a 2-1 (d/q) dq 15-0 oe# we# rp# t glqx t elqx valid address valid address valid address valid output valid output valid output valid output valid address v ih v il (a) a 22-3 valid address disabled (v ih ) enabled (v il ) (e) ce x v ih v il (f) byte# t fhqz t fhqv t elfh figure 7. ac waveform for 4-word page mode read operations (memory array) rev. 0.06 note: 1. memory array supports page mode read operations.
LHF64P01 23 rev. 0.06 figure 8. ac waveform for 8-byte page mode read operations (memory array) t avqv t elqv t ehqz t ghqz t oh t apa t phqv high z v ih v il v ih v il v oh v ol v ih v il (p) (w) (g) v ih v il (a) a 2-0 (d/q) dq 7-0 oe# we# rp# t glqx t elqx valid address v ih v il (a) a 22-3 valid address disabled (v ih ) enabled (v il ) (e) ce x v ih v il (f) byte# t flqz t elfl valid output valid output valid output valid output valid output valid output valid output valid output valid address valid address valid address valid address valid address valid address valid address t flqv t glqv note: 1. memory array supports page mode read operations.
LHF64P01 24 rev. 0.06 1.2.5 ac characteristics - write operations (1), (2) notes: 1. the timing characteristics for reading the status register during block erase, (page buffer) program, block lock configuration and otp program operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. a write operation can be initiated and terminated with either ce 0 , ce 1 , ce 2 or we#. 3. sampled, not 100% tested. 4. write pulse width low (t wp ) is defined from the first edge of ce 0 , ce 1 or ce 2 that enables the device or the falling edge of we# (whichever occurs last) to the first edge of ce 0 , ce 1 or ce 2 that disables the device or the rising edge of we# (whichever occurs first). hence, t wp =t wlwh =t eleh =t wleh =t elwh . 5. write pulse width high (t wph ) is defined from the first edge of ce 0 , ce 1 or ce 2 that disables the device or the rising edge of we# (whichever occurs first) to the first edge of ce 0 , ce 1 or ce 2 that enables the device or the falling edge of we# (whichever occurs last). hence, t wph =t whwl =t ehel =t whel =t ehwl . 6. v pen should be held at v pen =v penh until determination of block erase, (page buffer) program, block lock configuration or otp program success (sr.1/3/4/5=0). 7. refer to table 5 for valid address and data for block erase, (page buffer) program, block lock configuration and otp program. 8. the output delay time t avqv or t elqv is required in addition to t whgl (t ehgl ) for read operations after command writes. 9. the timing is defined from the first edge of ce 0 , ce 1 or ce 2 that enables the device. 10. the timing is defined from the first edge of ce 0 , ce 1 or ce 2 that disables the device. 11. sts timings depend on sts configuration. v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes min. max. unit t avav write cycle time 120 ns t phwl (t phel ) rp# high recovery to we# ( ce x ) going low 3, 9 1 s t elwl (t wlel )ce x (we#) setup to we# (ce x ) going low 90 ns t wlwh (t eleh )we# (ce x ) pulse width low 4, 9, 10 70 ns t dvwh (t dveh ) data setup to we# (ce x ) going high 7, 10 50 ns t av w h (t av e h ) address setup to we# (ce x ) going high 7, 10 55 ns t wheh (t ehwh )ce x (we#) hold from we# (ce x ) high 10 0 ns t whdx (t ehdx ) data hold from we# (ce x ) high 10 0 ns t whax (t ehax ) address hold from we# (ce x ) high 10 0 ns t whwl (t ehel )we# (ce x ) pulse width high 5, 9, 10 30 ns t vvwh (t vveh )v pen setup to we# (ce x ) going high 3, 10 0 ns t whgl (t ehgl ) write recovery before read 8 35 ns t whr0 (t ehr0 ) t whrl (t ehrl ) we# (ce x ) high to sr.7 going "0", sts going low 10, 11 500 ns t qvvl v pen hold from valid srd, sts high z 3, 6, 11 0 ns t flwh /t fhwh (t fleh /t fheh ) byte# setup to we# (ce x ) going high 10 50 ns t whfl /t whfh (t ehfl /t ehfh ) byte# hold from we# (ce x ) high 10 90 ns
LHF64P01 25 t avav t avwh (t aveh ) t whax (t ehax ) t elwl (t wlel ) t phwl (t phel ) t wlwh t whwl (t ehel ) t whdx (t ehdx ) t dvwh (t dveh ) t vvwh (t vveh ) t whqv1,2,3,4,5,6 (t ehqv1,2,3,4,5,6 ) t qvvl t wheh (t ehwh )t whgl (t ehgl ) v ih v il v ih v il v ih v il v ih v il (d/q) (w) (g) (a) a 22-0 dq 15-0 (v) v pen v ih v penh v penlk v il v il (p) rp# oe# we# v ih v il (f) byte# (t eleh ) valid address valid address valid address data in data in valid srd ("1") v ol (r) sts (sr.7) high z ("0") (t whr0 (t ehr0 )) t whrl (t ehrl ) disabled (v ih ) enabled (v il ) (e) ce x t flwh /t fhwh (t fleh /t fheh ) t whfl /t whfh (t ehfl /t ehfh ) note 1 note 2 note 3 note 4 notes 5, 6 notes 5, 6 notes: 1. v cc power-up and standby. 2. write each first cycle command. 3. write each second cycle command or valid address and data. 4. automated erase or program delay. this waveform illustrates the case when sts is in level mode (ry/by#). 5. read status register data. 6. for read operation, oe# and ce x must be driven active, and we# de-asserted. figure 9. ac waveform for write operations rev. 0.06
LHF64P01 26 t plph t plph t 2vph t plrh t phqv t phqv (a) reset during read array mode (b) reset during erase or program mode (c) rp# rising timing rp# rp# v il v ih v il v ih v cc gnd v cc (min) rp# v il v ih sr.7="1" v oh v ol (d/q) dq 15-0 valid output high z (p) (p) (p) v oh v ol (d/q) dq 15-0 valid output high z v oh v ol (d/q) dq 15-0 valid output high z t phqv t vhqv abort complete notes: 1. a reset time, t phqv , is required from the later of sr.7 (sts) going "1" (high z) or rp# going high until outputs are valid. refer to ac characteristics - read-only operations for t phqv . 2. the device may reset if t plph is <100ns, but this is not guaranteed. 3. sampled, not 100% tested. 4. if rp# asserted while a block erase, (page buffer) program, block lock configuration or otp program operation is not executing, the reset will complete within 100ns. 5. when the device power-up, holding rp# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there. reset ac specifications (v cc =2.7v-3.6v, t a =-40 c to +85 c) symbol parameter notes min. max. unit t plph rp# low to reset during read (rp# must be low during power-up.) 1, 2, 3 100 ns t plrh rp# low to reset during erase or program 1, 3, 4 30 s t 2vph v cc 2.7v to rp# high 1, 3, 5 100 ns t vhqv v cc 2.7v to output delay 31ms figure 10. ac waveform for reset operations rev. 0.06 1.2.6 reset operations
LHF64P01 27 rev. 0.06 1.2.7 block erase, (page buffer) program and block lock configuration performance (3) notes: 1. typical values measured at v cc =3.0v, v pen =3.0v and t a =+25 c. assumes corresponding lock bits are not set. subject to change based on device characterization. 2. excludes external system-level overhead. 3. sampled, but not 100% tested. 4. a latency time is required from writing suspend command (the first edge of ce 0 , ce 1 or ce 2 that disables the device or the rising edge of we#) until sr.7 going "1" or sts going high z. 5. if the interval time from a block erase resume command to a subsequent block erase suspend command is shorter than t eres and its sequence is repeated, the block erase operation may not be finished. 6. these values are valid when the page buffer is full, and the start address is aligned on a 16-word/ 32-byte boundary. 7. program time per byte (t whqv1 / t ehqv1 ) is 12.5 s/byte (typical). program time per word (t whqv2 / t ehqv2 ) is 25.0 s/word (typical). v cc =2.7v-3.6v, t a =-40 c to +85 c symbol parameter notes v pen =v penh unit min. typ. (1) max. page buffer program time (time to program 16 words/ 32 bytes) 2, 6, 7 400 1200 s t whqv3 / t ehqv3 program time 2 210 630 s block program time (using page buffer program command) 21.64.8s t whqv4 / t ehqv4 block erase time 2 1 5 s t whqv5 / t ehqv5 set block lock bit time 2 64 85 s t whqv6 / t ehqv6 clear block lock bits time 2 0.5 0.7 s t whrh1 / t ehrh1 (page buffer) program suspend latency time to read 42590 s t whrh2 / t ehrh2 block erase suspend latency time to read 42640 s t eres latency time from block erase resume command to block erase suspend command 5 600 s
LHF64P01 28 rev. 0.06 2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales offices. document no. document name fum03201 lh28f640sp series appendix

lh28f640spxx-xxxxx flash memory errata 1. table 5. command definitions problem while block erase or (page buffer) program is being suspended by issuing block erase and (page buffer) program suspend command, memory array data can not be normally read by issuing read array command. workaround block erase and (page buffer) program suspend command should not be issued. status this is intended to be fixed in future devices. 031002 i
030313 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph gnd v cc (min) rp# v il v ih (p) t phqv v pen *1 gnd v penh (v) we# v il v ih (w) oe# v il v ih (g) v oh v ol (d/q) data high z valid output t vr t f t elqv t f t glqv (a) address valid (rst#) (v pp ) t r or t f address v il v ih t avqv t r or t f t r t r *1 to prevent the unwanted writes, system designers should consider the design, which applies v pen (v pp ) to 0v during read operations and v penh (v pph ) during write or erase operations. (v pph ) see the application note ap-007-sw-e for details. disabled (v ih ) enabled (v il ) (e) ce x v cc v ccq
030313 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v
030313 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ? dc characteristics ? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises
030313 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit

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